l l l l l l l l l l l Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications Supports PC-100 and Meets “PC100 SDRAM registered DIMM Specification Rev. 1.2.
Supports PC-100 and Meets “PC100 SDRAM registered DIMM Specification Rev. 1.2” Distributes One Clock Input to One Bank o.
The HC2510C is a
low-skew, low jitter, phaselocked loop(PLL) clock driver, distributing high frequency clock signals for SDRAM. The HC2510C operates at 3.3V Vcc and provides integrated series-damping resistors that make it ideal for driving point-to-.
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